[myhdl-list] Another MyHDL powered Soft Processor and some bugs in MyHDL

[Jian L. <jia...@go...>]

Hi List,

I've uploaded my recent Soft Processor Project on opencores. It's a
synthesizable clone of MicroBlaze called myBlaze.
The Hello world and fibonacci tests runs well on the spartan3e starter kit
with uart as the default output.

Here is the project homepage: http://opencores.org/project,myblaze
I'll write some instructions when I get time. However, I believe, the code
mostly explains itself.

And during the coding, I might just find two bugs in MyHDL conversion:
1. Name of a ram type won't be convert correctly in user defined verilog
(and might be in vhdl too).
  A dirty workaround is to subclass list like this:

  .def RAMInitial(ram, filename, clock):
  .    __verilog__ = """
  .    initial $readmemh("%(filename)s", %(ram)s);
  .    """
  .    __vhdl__ = """
  .    """
  .    @instance
  .    def initial():
  .        vals = open(filename).readlines()
  .        for i,v in enumerate(vals):
  .            ram[i].next = int(v, 16)
  .        yield clock.negedge
  .    return instances()
  .
  .# XXX: Hacked to make $readmemh work
  .class RAM(list):
  .    # representation
  .    def __str__(self):
  .        from myhdl._extractHierarchy import _memInfoMap
  .        if id(self) in _memInfoMap:
  .            return _memInfoMap[id(self)].name
  .        else:
  .            return list.__str__(self)

  and use RAM, RAMInitial to define and initialize a ram.

  So far, it works for me both in Xilinx ISE and Altera Quartus II. But I
think it would be nice if myhdl supports initial value by default.
  Any plan, Jan?

2. if __debug__: instructions seems broken in top level hierarchy. Code like
following doesn't work as expected:

  . def ExampleDummy(x, y):
  .    ...
  .    if __debug__:
  .        return z
  .    return z, debug_logic

  but if I wrap it as a instance in some higher modules, it works again. My
guess is: analyze process just overlooks such situation.


Gruss

Jian