[myhdl-list] project finished
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From: Martín G. <ga...@gm...> - 2010-11-20 05:55:42
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I've just finished my project (the DLX/MIPS processor) and its report. I have no feedback from the lab teacher yet (of course, I've just sent it ... and it's saturday) but I think it's working fine. The experience with MyHDL was very successfully . At the beginning the learning curve was a bit steep , because more than one, really: MyHDL itself, HDL's in general and the DLX architecture in particular. But, clearly, was nothing impossible. I don't know if a comparison is valid because I was specially rushed to get it done, but everybody else at the course are still fighting with testbenchs in VHDL and the abusive consumption of RAM of the Xilinx's IDE. I don't know if I'll use MyHDL again sometime in the future (never say never) but I would like to contribute to the project in some way. For example, translating or writing an article about it. I found this article in portuguese, http://www.cin.ufpe.br/~cinlug/wiki/index.php/Hardware_myhdl_python what do you think about translate it to spanish ? Are the the author, Rodrigo Peixoto, in this list? May be something more updated ? Cheers Martin |