[myhdl-list] How does traceSignals find its signals?

[<as...@gm...>]

I'm an experienced Python programmer but a novice with modern HDLs.
I'm trying MyHDL because of its potential to make very sophisticated
test benches.  But I'm having difficulty using traceSignals.  My
circuit simulates fine, but the resulting .vcd file contains no
signals at all.  Is the unittest framework somehow confusing
traceSignals?

#! /usr/bin/python

import unittest

from myhdl import *

def dff(D, Q, CLK):
  """A D flip flop"""
  @always(CLK.posedge)
  def process():
    Q.next = D
  return process


class TestDFF(unittest.TestCase):
  def setUp(self):
    self.D = Signal(False)
    self.Q = Signal(False)
    self.CLK = Signal(False)
    self.inst = dff(self.D, self.Q, self.CLK)

  def testDff(self):
    @instance
    def dff_tb():
      yield delay(1)
      self.CLK.next = True
      yield delay(1)
      self.assertEqual(self.Q, False)
      self.CLK.next = False
      yield delay(1)
      self.D.next = True
      yield delay(1)
      self.CLK.next = True
      yield delay(1)
      self.assertEqual(self.Q, True)
    def foo():
      return dff_tb, self.inst
    foo_tb = traceSignals(foo)
    sim = Simulation(foo_tb)
    sim.run(quiet=True)

unittest.main()