Re: [myhdl-list] compiling generated VHDL code

[Martín G. <ga...@gm...>]

On Thu, Oct 28, 2010 at 2:46 AM, Christopher L. Felton
<chr...@gm...> wrote:
> This might help, from the MyHDL manaul the default simulator for VHDL is
> GHDL.  You can see in the default config you need to inlcude the
> pck_myhdl_*.vhd file as well.
>
>

Thanks Chris, but that appears not work.

(hdl)tin@azulita:~/facu/arq/project/vhdl$ ghdl -a pck_myhdl_06.vhd alu.vhd
alu.vhd:31:22: no function declarations for operator "and"
alu.vhd:33:22: no function declarations for operator "or"
/usr/lib/ghdl/bin/ghdl: compilation error

I also replaced toVHDL() to compile.analyze on the python code, and I
get the same compilation error but a failed* testbench  also.

(*) all output are always 0, which is wrong


(hdl)tin@azulita:~/facu/arq/project$ python alu.py
/usr/lib/python2.6/sets.py:85: DeprecationWarning: functions
overriding warnings.showwarning() must support the 'line' argument
  stacklevel=2)
** DeprecationWarning: the sets module is deprecated
/home/tin/.virtualenvs/hdl/lib/python2.6/site-packages/myhdl-0.6-py2.6.egg/myhdl/conversion/_toVHDL.py:219:
DeprecationWarning: functions overriding warnings.showwarning() must
support the 'line' argument
  category=ToVHDLWarning
** ToVHDLWarning: Output port is read internally: out_
alu.vhd:31:22: no function declarations for operator "and"
alu.vhd:33:22: no function declarations for operator "or"
/usr/lib/ghdl/bin/ghdl: compilation error
Analysis failed
Control: 0000 | 251 AND 150 | 0 | z=0
Control: 0001 | 196 OR 100 | 0 | z=0
Control: 0010 | 187 add 56 | 0 | z=0
Control: 0110 | 167 substract 185 | 0 | z=0
Control: 0111 | 79 set on < 214 | 0 | z=0
Control: 1100 | 167 NOR 231 | 0 | z=0
<class 'myhdl.StopSimulation'>: No more events
(hdl)tin@azulita:~/facu/arq/project$

any other idea?