Re: [myhdl-list] List of signals unsupported in top-level instance in toVHDL

[Jan D. <ja...@ja...>]

Sigve Tjora wrote:
> Hi,
> input or output-signals in list are silently ignored in toVHDL. Is there 
> something I do wrong in my small example? 

No, this was a bug.

The problem is that Verilog doesn't permit memories as ports.
As my goal is to support both Verilog and VHDL equally, I have
to use the lowest common demoninator. Therefore, list of signals
as ports are not supported.

I don't think this a very large problem in practice - it is
only a restriction at the very top level, not when such a
module is used internally (thanks to the hierarchical flattening
by the convertor.) Verilog has done without this for over
25 years :-)

Based on your example (thanks) I have added an error check
and a unit test to avoid this, and pushed it to the public repo's.

Jan


I have not found any method to 
> fix this other than to change the generated vhdl-file after generation.
> 
> Sigve
> 
> An example:
> 
> from myhdl import *
> 
> def my_register(clk, input, output):
>     @always(clk.posedge)
>     def my_register_impl():
>         for index in range(len(input)):
>             output[index].next = input[index]
>     return my_register_impl
> 
> def my_register_to_vhdl():
>     count = 3
>     clk = Signal(False)
>     input = [Signal(intbv(0)[8:0]) for index in range(count)]
>     output = [Signal(intbv(0)[8:0]) for index in range(count)]
>     
>     toVHDL(my_register, clk, input, output)
>     
> if __name__=="__main__":
>     my_register_to_vhdl()
> 
> 
> generates the following VHDL without any warnings or errors:
> -------------------------------------------------------------------------------------------------------------------------------------------------------------
> -- File: my_register.vhd
> -- Generated by MyHDL 0.7dev
> -- Date: Mon Oct 18 19:44:40 2010
> 
> 
> library IEEE;
> use IEEE.std_logic_1164.all;
> use IEEE.numeric_std.all;
> use std.textio.all;
> 
> use work.pck_myhdl_07dev.all;
> 
> entity my_register is
>     port (
>         clk: in std_logic
>     );
> end entity my_register;
> 
> 
> architecture MyHDL of my_register is
> 
> type t_array_output is array(0 to 3-1) of unsigned(7 downto 0);
> signal output: t_array_output;
> type t_array_input is array(0 to 3-1) of unsigned(7 downto 0);
> signal input: t_array_input;
> 
> begin
> 
> MY_REGISTER_MY_REGISTER_IMPL: process (clk) is
> begin
>     if rising_edge(clk) then
>         for index in 0 to 3-1 loop
>             output(index) <= input(index);
>         end loop;
>     end if;
> end process MY_REGISTER_MY_REGISTER_IMPL;
> 
> end architecture MyHDL;
> 
> -------------------------------------------------------------------------------------------------------------------------------------------------------------
> The code I would expect is something like:
> 
> -------------------------------------------------------------------------------------------------------------------------------------------------------------
> -- File: my_register.vhd
> -- Generated by MyHDL 0.7dev
> -- Date: Mon Oct 18 19:47:05 2010
> 
> 
> library IEEE;
> use IEEE.std_logic_1164.all;
> use IEEE.numeric_std.all;
> use std.textio.all;
> 
> use work.pck_myhdl_07dev.all;
> 
> entity my_register is
>   port (
>     clk    : in  std_logic;
>     input  : in  array(0 to 3-1) of unsigned(7 downto 0);
>     output : out array(0 to 3-1) of unsigned(7 downto 0)
>     );
> end entity my_register;
> 
> architecture MyHDL of my_register is
> 
> begin
> 
>   MY_REGISTER_MY_REGISTER_IMPL : process (clk) is
>   begin
>     if rising_edge(clk) then
>       for index in 0 to 3-1 loop
>         output(index) <= input(index);
>       end loop;
>     end if;
>   end process MY_REGISTER_MY_REGISTER_IMPL;
> 
> end architecture MyHDL;
> 
> 
> ------------------------------------------------------------------------
> 
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-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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