Re: [myhdl-list] Blog post about Verilog

[Jan D. <ja...@ja...>]

Andrew Stone wrote:
> Hi Jan,
> 
> I'm a dabbler at HDL but am experienced at software on von-neumann 
> machines and well, I feel like I can just barely NOT follow what you are 
> trying to say :-(.  Which is a lot more frustrating than it being 
> completely over my head.

Perhaps this means I have achieved my goal: in VHDL (and MyHDL), you
don't really have to worry about these matters as a designer.

But in Verilog, it you are not aware of all this, you are in for
big trouble sooner or later.

It's a difference that is seldom talked about, but I think language
decision makers should be aware of.

> I would think that any reasonable simulator would execute concurrent 
> hardware in random order, or multiple times in multiple orders (and 
> compare the outputs), or even better, model each bit as "1", "0" or 
> "undetermined" -- i.e. in the process of being changed -- and raise a 
> BIG flag if you access an "undetermined" bit! :-).  I'm guessing from 
> your post that that is not the case.

No. VHDL's contribution is that it guarantees determinism, even though
the processes are executed in random order. Verilog has no such guarantee,
so a designer has to take his own measures. For all kinds of reasons,
including language history, that's not an obvious task.

BTW, MyHDL is mostly like VHDL in this respect, with one big exception:
it doesn't have resolution functions like in VHDL, so when you drive
a signal from several processes, the result will be non-deterministic.

> If you are targeting the blog for wider audiences, maybe a quick 
> definition of what synchronous RTL design IS, maybe an example of when 
> you would use it.  Also some verilog code snippets would really help! concepts.


My target audience are hardware designers who consider themselves
relatively experienced, and my goal is to challenge their conventional
wisdom. I don't think there's a lack of tutorial-level info, but
there definitely is a lack of critical and historical review of the
concepts.

> Also I am confused about whether the simulator's non-deterministic 
> behaviour is caused because your code is actually non-deterministic on 
> the chip...

The two are not really related. For digital design to be
possible, it should be deterministic. A lot of what is done when
developing silicon processes or gate-level libraries is related
to this. How a simulator supports determinism is another matter.
VHDL does it automatically, Verilog makes it surprizingly hard.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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