[myhdl-list] Verilog blocking assignments in combinatorial logic

[Jan D. <ja...@ja...>]

Recently I found out that Verilog non-blocking assignments were
less general as I though w.r.t preventing non-determinism.

This weakens my earlier position to use non-blocking assignments
everywhere for communication, also in combinatorial logic.

I propose to give in and use blocking assignments in combinatorial
logic by default. (There is a new configuration attribute to control this.)

Objections, anybody? I guess not.

Jan

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