Re: [myhdl-list] Verilator as a backend to myhdl?
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jandecaluwe
From: Jan D. <ja...@ja...> - 2010-10-07 18:57:58
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Terry Chen wrote: > Hi myhdl developers, > > I am new to the mailing list. So I am not sure if this issue has already > been discussed. I tried searching the mailing list archive, but didn't > find anything similar. > > My question is: has anyone attempted to use a verilated C model (from > wilson snyder's verilator) as the backend simulator for myhdl through > some sort of python-to-C foreign language interface? > > The motivation behind this is that I would like to combine the > high-level programming power of python (and myhdl) with the speed of > verilator. I could use co-sim w/ icarus or cver, but I find that > cosimulation time is prohibitively slow. Commercial simulator (we use > modelsim) are acceptably fast, but we have a limited number of licenses, > and we can't afford to use them to run regressions. > > Any thoughts / comments would be much appreciated. I fear that as long a you would have Python somewhere in the loop, it will quickly be the limiting factor in your simulation. Ultra-fast regression type simulation just doesn't match very well with super high-level programming power. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com |