[myhdl-list] Blog post about Verilog

[Jan D. <ja...@ja...>]

For those interested, I have blogged about my
experiences with Verilog. They explain some design
decision in MyHDL.

http://www.sigasi.com/content/verilogs-major-flaw

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
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