Re: [myhdl-list] Signals only read and written from custom __vhdl__

[Jan D. <ja...@ja...>]

Sigve Tjora wrote:
> Hi everybody,
> I have problems with myhdl not generating all the needed signal 
> declarations in VHDL. What I have found so far, is that if a signal is 
> written from a custom 
> __vhdl__ block and only read from custom __vhdl__ blocks, I need to call
> 
> _markUsed() on the signal to have the signal declaration generated in VHDL.
> 
> and
> _markRead() to suppress the myhdl warning on signal not being read 
> anywhere in the design.
> 
> Is this the correct way to do this? I feel a bit bad when using private 
> functions on objects, is there a official way to achieve something similar?

Yes, the 'driven' attribute.

http://www.myhdl.org/doc/current/manual/conversion.html#user-defined-code

Note that for VHDL it only counts whether the attribute is true or not,
for Verilog it also specifies the type of object being driven.

There is also a currently undocumented public 'read' attribute, with
the expected effect.

Let me know how it goes. I'm not entirely happy with this. Ideally
I think these attributes should work as a hint, but not be used in
error detection as currently is the case. For example, it you set the
'driven' attribute redundantly, and the convertor can also infer that
the signal is in fact driven, you currently will get a 'multiple driven'
error now. 

Jan

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