Re: [myhdl-list] Development status update

[Jan D. <ja...@ja...>]

Jan Decaluwe wrote:
> Patricio Kaplan wrote:
>> Jan,
>>
>> have you tried verilator for verilog? it is actively maintained and as 
>> far as I can tell doing a very good job.
> 
> No, from their overview info I concluded that is was not a
> solution for my purposes.
> 
> I just checked the website again. Apparently their value proposition
> is to make synthesizable code run very fast. But that's not what
> I need. I need full, trustworthy language support and for the unit
> tests I really don't care about performance.
> 
> MyHDL can now convert much, much more than synthesizable logic.
> I use it to convert reasonably complex python unit tests,
> thereby bypassing simulation.
                    ^
            I meant CO-simulation


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com