Re: [myhdl-list] Saying Hi from Argentina

[Jan D. <ja...@ja...>]

Martín Gaitán wrote:
> Hi everybody.
> 
> this is the situation: I'm a student  with one subject left (and the 
> final project, which it's almost cooked [1])  to get a dregree Computer 
> Engineering [2] at Córdoba, Argentina. This subject is computer 
> architecture. To pass and be happy I must implement a DLX/MIPS pipelined 
> processor. I would like to get my degree someday in the rest of 2010.
> I forget what I ever knew about VHDL and I never knew Verilog. but I 
> enjoy very much programming python.
> 
> My gantt diagram says that I have a month to do this.  Do you think 
> MyHDL it's my workhorse ?

Using MyHDL for a project like this shouldn't pose any problem,
has the advantage that you can use python for testing, and that
you end up with both Verilog and VHDL for the same effort.

Main problem is the specs and testing strategy probably.

For example - what if you just download VHDL or Verilog code
that is apparently easy to find, and submit it?
I assume that your teachers expect some amount of originality
from you, but how do they define that?

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com