[myhdl-list] Saying Hi from Argentina

[Martín G. <ga...@gm...>]

Hi everybody.

this is the situation: I'm a student  with one subject left (and the final
project, which it's almost cooked [1])  to get a dregree Computer
Engineering [2] at Córdoba, Argentina. This subject is computer
architecture. To pass and be happy I must implement a DLX/MIPS pipelined
processor. I would like to get my degree someday in the rest of 2010.
I forget what I ever knew about VHDL and I never knew Verilog. but I enjoy
very much programming python.

My gantt diagram says that I have a month to do this.  Do you think MyHDL
it's my workhorse ?

seriously, I'll be bothering here for a while. be patience. and thanks in
advance.

BTW, any open source MIPS-like project in MyHDL over there?



[1] http://code.google.com/p/gpec2010/
[2] http://computacion.efn.uncor.edu/  (probably a 404, the net an its
admins sucks)