Re: [myhdl-list] How to give signals custom names in toVHDL

[Sigve T. <pu...@tj...>]

2010/9/21 Jan Decaluwe <ja...@ja...>:
> Sigve Tjora wrote:
>>>> I have a problem where different signals get the same name in VHDL
>>>> when using toVHDL, caused when using two instances with identical
>>>> names according to _makeName.
>>> How can 2 different instances have the same name?
>>> (except in another part of the hierarchy, where the hierarchical
>>> name is different).
>>
>> I was thinking about recreating the bug with a simple example, but
>> found the bug in the process. As it is easier to explain the bug and a
>> possible fix, I will do that.
>>
>> The problem is in the conversion._analyze._analyzeSigs function:
>>
>>         # skip processing and prefixing in context without signals
>>         if not (sigdict or memdict):
>>             prefixes.append("")
>>             continue
>>         prefixes.append(name)
>>
>> This adds an empty prefix if the current context has no signals. If
>> the hierarchy names are the same on both sides on this context,
>> signals-names will clash. A possible fix is to replace the code above
>> with:
>>
>>         # skip processing and prefixing in context without signals
>>         prefixes.append(name)
>>         if not (sigdict or memdict):
>>             continue
>>
>> This inserts the name of all contexts in the prefixes list, even if
>> the context has no signals.
>
> This may certainly be a case of premature optimization. But I
> think I still need an example.
I am working reproducing the error in a simple example, but has not
managed to do that yet. I am not familiar enough with the inner
workings of MyHdl to easily figure out what triggers the error.

> With "both sides" I think you mean a higher and a lower level in the hierarchy.
Correct.

> The lower level should still have an additional hierarchical prefix?
This is also correct, but the problem is when returning a list of
instances, where all the instances is similar. If this list is
"my_inverters", the resulting names for a given hierarchy should be

toplevel_my_inverters_0_register_output
toplevel_my_inverters_1_register_output
toplevel_my_inverters_2_register_output

but for my case the sigdict and memdict (in _analyzeSigs) is empty for
each my_inverters-instance, causing the generated names to collapsed
to:
toplevel_register_output
toplevel_register_output
toplevel_register_output

causing the name clash.

I have not yet figured out why the sigdict is empty for my case.

Sigve