Re: [myhdl-list] How to give signals custom names in toVHDL

[Jan D. <ja...@ja...>]

Sigve Tjora wrote:
>>> I have a problem where different signals get the same name in VHDL
>>> when using toVHDL, caused when using two instances with identical
>>> names according to _makeName.
>> How can 2 different instances have the same name?
>> (except in another part of the hierarchy, where the hierarchical
>> name is different).
> 
> I was thinking about recreating the bug with a simple example, but
> found the bug in the process. As it is easier to explain the bug and a
> possible fix, I will do that.
> 
> The problem is in the conversion._analyze._analyzeSigs function:
> 
>         # skip processing and prefixing in context without signals
>         if not (sigdict or memdict):
>             prefixes.append("")
>             continue
>         prefixes.append(name)
> 
> This adds an empty prefix if the current context has no signals. If
> the hierarchy names are the same on both sides on this context,
> signals-names will clash. A possible fix is to replace the code above
> with:
> 
>         # skip processing and prefixing in context without signals
>         prefixes.append(name)
>         if not (sigdict or memdict):
>             continue
> 
> This inserts the name of all contexts in the prefixes list, even if
> the context has no signals.

This may certainly be a case of premature optimization. But I
think I still need an example. With "both sides" I think you
mean a higher and a lower level in the hierarchy. The lower
level should still have an additional hierarchical prefix?


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