Re: [myhdl-list] myhdl array signals initialization not initialized in vhdl array.
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jandecaluwe
From: Jan D. <ja...@ja...> - 2010-09-15 17:40:43
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Sverre Hamre wrote: > Hello. > > I have an issue where initialized signals in myhdl arrays is not > initialized in the vhdl code. > > I added a simple example code and the generated vhdl output files. > > In the vhdl outputfile the signal using the array is not initialized, > since the signals in the myhdl array is initialized I would expect the > vhdl array to be initialized also. Is this a bug? or am I missing > something her. This currently doesn't work for plain signals either. The proper way would be include initializations with the signal or array declarations. I had once done that, but removed it again because some synthesis tools didn't support is. If we are sure that it's no problem for synthesis tools (including Xilinx and Altera), we can consider to put it in again. > I am using myhdl-0.7.1134 > > Thank you and please cc me as I am not subscribing the list. Note that you can follow and post to the list as a newsgroup without subscribing. http://www.myhdl.org/doku.php/mailing_list -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com |