Re: [myhdl-list] Model a PFD

[Christopher L. F. <chr...@gm...>]

On 7/25/2010 5:43 AM, Thomas Heller wrote:
> I'm trying to model a phase frequency detector like the one
> in Figure 1 of this article:
>
> http://www.analog.com/library/analogDialogue/archives/33-07/phase3/
>
> IMO the VHDL code would be something like this:
>
> process(in_a, in_b, up, down)
> begin
>    if up = '1' and down = '1' then
>      up<= '0';
>      down<= '0';
>    else
>      if rising_edge(in_a) then
>        up<= '1';
>      end if;
>      if rising_edge(in_b) then
>        down<= '1';
>      end if;
>    end if;
> end process;
>
> How would I code this in myhdl?
>
>    
In your VHDL process you specify 3 signals in the sensitivity list.   
Two of the signals are qualified to be rising edge sensitive.  In MyHDL 
you can do the similar thing.

@always(in_a.posedge, in_b.posedge, up, down)
def rtl_pfd():
     if up and down:
         up.next = False
         down.next = False
     if in_a:
         up.next = True
     if in_b:
         down.next = True


I didn't test the above, I need to double check the the level sensitive 
syntax is @always(sig, sig, ...).

> Looking at the what's new in myhdl 0.6 document, section 1.3.4,
> I see no possibility to distinguish the rising edge of in_a from
> the rising edge of in_b...
>
>