[myhdl-list] Model a PFD

[Thomas H. <th...@ct...>]

I'm trying to model a phase frequency detector like the one
in Figure 1 of this article:

http://www.analog.com/library/analogDialogue/archives/33-07/phase3/

IMO the VHDL code would be something like this:

process(in_a, in_b, up, down)
begin
  if up = '1' and down = '1' then
    up <= '0';
    down <= '0';
  else
    if rising_edge(in_a) then
      up <= '1';
    end if;
    if rising_edge(in_b) then
      down <= '1';
    end if;
  end if;
end process;

How would I code this in myhdl?

Looking at the what's new in myhdl 0.6 document, section 1.3.4,
I see no possibility to distinguish the rising edge of in_a from
the rising edge of in_b...

-- 
Thanks,
Thomas