Re: [myhdl-list] hg rev 1105 : better support for mapping to case statements
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From: Jan D. <ja...@ja...> - 2010-07-22 09:45:40
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Christopher Felton wrote: > I apologize for the lack of information up front. I updated to the > latest tip to check out some of the changes. I ran into an issue. > > I believe it is related to the changes checked into revision 1105 > (better support for mapping to case statements). I reverted back to > 1104 and the issue didn't occur. > > The issue/error was an invalid casez statement (?). At least Icarus > determined it invalid "error: Unable to bind wire/reg/memory `False' in". I have found and fixed bug related to this. The background is that I'm trying to infer Verilog case statements more often, not only when using enums but also when testing an intbv against a number of integer values. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com |