[myhdl-list] model a delay line?

[Thomas H. <th...@ct...>]

I want to simulate such a triggerable oscillator (hope you can read my ascii art;
it is a nor-gate with a delay line connecting the inverting output with an input):

           -------
        --( delay )---- 
       |   -------     |
       |               |
       |   \---        |
        ----\   \O----- 
             )   )
input >-----/   /----------------->  output
           /---

Does someone have an idea about how I can simulate the delay line?

-- 
Thanks,
Thomas