Re: [myhdl-list] Deterministic output of toVHDL

[Jan D. <ja...@ja...>]

Knut Eldhuset wrote:
> Hi all,
> 
> I would like the output of toVHDL to be deterministic, meaning the 
> generated .vhd files should be identical when nothing has changed 
> between runs. At least two things are non-deterministic in default branch:
> 
> 1) The timestamp is included in output files.
> 2) The order of enum typedefs in package declarations is random.
> 
> 1) is easily fixed by monkey-patching datetime, but this is not an ideal 
> solution.

I have recently pushed a changeset to the development repo that lets
you define your own header (brand new - undocumented, see the source.)

With toVHDL.suppress_myhdl_header = False, you can suppress the default header.

With toVHDL.header = <string.Template argument> you can set your own header.

The default header is defined as follows:

myhdl_header = """\
-- File: $filename
-- Generated by MyHDL $version
-- Date: $date
"""

and you can use the same keys in your own header, it is processed by string.Template.
Same for toVerilog.


> 
> 2) can be fixed by sorting the enum typedefs by name before emitting 
> them. (I have a patch if interested)

Yes, provided it is a mercurial bundle or patch.

Thanks,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com