Re: [myhdl-list] Proposal: better support for hierarchy and user-defined code

[Jan D. <ja...@ja...>]

Angel Ezquerra wrote:

> Jan, if you don't mind could you explain a bit further
> whether there are technical reasons to not replicate the 
> python function hierarchy when you generate the VHDL or
> Verilog code? That is, why use this 2-step approach and
> not simply generate hierarchy code by default? Are there
> some hidden drawbacks that I don't understand? I am still
> trying to fully understand how myhdl conversion works, so
> maybe there is something obvious that I did not get!

The most important reason is not technical.

The idea behind conversion is to use Verilog or VHDL as 
back-end languages that for advanced MyHDL users eventually
disappear in the process - just some automated step in
a Makefile. Having a single file instead of a whole bunch
of files depending on the status of your design, just
makes this a tad more transparent.

(I realize that I'm working hard against this with
nicely formatted code, and now the documentation forwarding,
but still. It's the difference between attracting new
users and the eventual goal.)

Hierarchy is useful for human designers and debuggers,
but up to several 100Ks of gates, not necessarily to tools.
(Actually one well-known way to get better synthesis is by
removing more hierarchical boundaries.)

That having said, flattening out the hierarchy is really
the simplest and most straightforward way to get the
output, so this works in the same direction.

> Sorry, I do not get exactly what would be the use case
> for the "verilog_instance" attribute.

Semi-automatic hierarchy. Just give a name and you get
the instantiation, instead of having to write the instantiation
template yourself. Note that this gives you fine-grained
control of where you want to put the hierarchical boundaries.

> I think that this attribute based approach is a very 
> promising. Could this be used to allow you to define 
> libraries that must be used when using user generated code?
> 
> What I mean is that you could have another pair of attribures,
> mamed "vhdl_libraries" and "verilog_libraries", for example, 
> which you could use to define some libraries that you must add
> when you generate the vhdl or verilog code (as discussed in
> one of the recent threads?). Or maybe this could be used for
> something even more generic (i.e. not only for library 
> declarations).

All possible, but let's first see if this is really the
best way to handle technology libraries, see other threads.

Jan


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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