Re: [myhdl-list] Adding library declarations to your VHDL code

[Angel E. <ang...@gm...>]

Jan Decaluwe <jan <at> jandecaluwe.com> writes:

> 
> Angel Ezquerra wrote:
> > I am trying to make a myhdl block that will let me introduced a 
> > Xilinx DSP48e block.
> > 
> > In order to use and simulate this block you must add the following 
> > library use
> > declaration before the declaration of the entity that will use 
> > the DSP48 block:
> > 
> > Library UNISIM;
> > use UNISIM.vcomponents.all;
> 
> Actually, before the architecture declaration I guess (so that the entity
> could be kept technology-independent).

I was actually following Xilinx' advice. I am basically trying to create
MyHDL wrappers for some of the macros and templates that are provided
by Xilinx in their ISE Project Navigator tool. In those templates they say:

    --  Copy the following two statements and paste them before the
    --  Entity declaration, unless they already exist.

    Library UNISIM;
    use UNISIM.vcomponents.all;
 
I have never tried doing otherwise. You think that should work?
 

> > I have the following questions:
> > - Is there a way to tell myhdl that a certain entity
> >  requires a certain set of libraries?
> 
> Currently there is no option to add libraries to the output. Probably
> this should be added as an attribute to toVHDL().

Do you mean that you would pass the libraries as an additional argument
to ToVHDL? Or do you mean that there could be some additional magic 
variable or attribute, similar to the current __vhdl__ "magic" variable 
or to the recently proposed vhdl_code attribute (perhaps named
__vhdl_libraries__ or something similar)? You would set that new attribute
on the MyHDL source code, which would then be picked up by the ToVHDL() 
function.

I'd very much prefer the second option, since it would ensure that
all dependencies of a certain component are specified right where you
define that component. Also it would let you use different libraries
for different entities.

Is that what you had in mind?


> > - I created a "dummy" entity that simply contains the DPS48E 
> > instance
> > declaration and maps the input ports to the DSP48E instance ports:
> > 
> >    - Is that the right approach?
> 
> I think this could be a good way to isolate technology dependent
> stuff as much as possible.

Nice. My idea is to create a myhdl.xilinx package. This package could
have several subpackages like virtex6, virtex5, etc. To use any of
the Xilinx specific blocks in a MyHDL design one would simply need
to do "from myhdl.xilinx.dsp48 import multiplier" or
"from myhdl.xilinx.cpld.bufg", etc. Device specific blocks
(i.e. devices which are only found in virtex5, etc) could go
into their own subpackages (I am still thinking about the details).

But before I can do that I must make sure that it is actually doable,
so any advice or support on your end would be appreaciated.


> >    - Is it possible to force the port types
> 
> If the conversion doesn't do it right, you can set the
> signal.driven (documented in the manual) and the 
> signal.read (undocumented I believe) attributes in
> the module yourself, to infer the proper port type.

The MyHDL documentation for the "driven" attribute says that
it can have two possible values: "reg" and "wire". The documentation
only talks about verilog. Since I do not know much verilog
but if I recall properly the difference is related to whether a
variable is given its value by behavioural or structural code. In
both cases MyHDL sets the port type to inout, so I guess it does
not matter which one you use, right?

On the other hand, what are the valid values for the "read" attribute?


> >    ? MyHDL seems to be creating them as
> > "inout"
> 
> This would normally mean that you both drive and read a signal
> in a module. (Note: Verilog support reading from output ports.)

Actually, I have realized that this was a problem with my code, not
a MyHDL problem.

I was blindly following the example in the myhdl documentation page
without really understanding it! In the example the "driven" attribute
of the input port was being set to "wire". This made my clock port
be declared as inout by the MyHDL conversion.

 
> >    - Can I make some ports optional (and give them default values?
> >    - Should I declare the generics (i.e. the "generic map" part 
> >      as regular python function arguments?
> > 
> > Sorry if these questions are very basic. I did not find (or 
> > perhaps understand) the corresponding information on the 
> > User-Defined code part of the MyHDL documentation.
> 
> I'm not aware of a standard systematic approach currently -
> research more than welcome. The ideal approach may depend
> on the case. MyHDL probably lacks some features, or documentation,
> as discussed above, to support certain realistic use cases.
> Also, there is the question where to put boundary of the
> parametrization, more to Python, or more to VHDL (e.g. by
> using multiple architectures.)

I am not sure what you are suggesting here. How do you propose
to generate more than one architecture from MyHDL?

Cheers,

Angel