Re: [myhdl-list] full case / parallel case

[Christopher F. <chr...@gm...>]

On Mon, Jun 21, 2010 at 7:06 PM, Jan Decaluwe <ja...@ja...> wrote:

> Currently the Verilog convertor outputs
> the synthesis directives full case / parallel case.
> It's an old thing, originally intended to make designs
> with case statements more optimal.
>
> I have read a paper that advocates against this,
> and I agree. A good synthesis tool should be able
> to infer these semantics from the code itself.
> If that's not possible, it means that there is a risk
> for simulation/synthesis mismatch.
>
> So I propose to remove these directives.
> Any objections?
>
>
>
No objection here, feel free to remove.

.chris