[myhdl-list] full case / parallel case

[Jan D. <ja...@ja...>]

Currently the Verilog convertor outputs
the synthesis directives full case / parallel case.
It's an old thing, originally intended to make designs
with case statements more optimal.

I have read a paper that advocates against this,
and I agree. A good synthesis tool should be able
to infer these semantics from the code itself.
If that's not possible, it means that there is a risk
for simulation/synthesis mismatch.

So I propose to remove these directives.
Any objections?


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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