Re: [myhdl-list] if-elif to case conversion

[Jan D. <ja...@ja...>]

Jian LUO wrote:
> Hi Jan,
> 
> I found the conversion from if-elif-else to case doesn't work in 0.7dev 
> anymore,
> and tried to fix it.
> So far I got Verilog version work, but toVHDL still fails. 
> Maybe you can find a clue, why it doesn't work.

Thanks for debugging.

As it turns out, the whole if-elif thing was still completely
broken in development. 

The problem is that the old compiler package had a flat
representation of an if-elif tree, while the new ast package
represents it as a tree. For things like template transformation
(VHDL) and if-to-case mapping, the flat representation is
much easier. Therfore, my idea was to convert the tree
into the old representation and keep the old code. But
the flattening code was broken.

I have started by applying your patch, and then continued
to fix the problem. The flattening has been rewritten
completely.

One problem is that ast doesn't make a difference between:

   if rst == 0:
       q.next = 0
   else
      if en:
          q.next = 0

and:

   if rst == 0:
       q.next = 0
   elif en:
       q.next = 0

while the compiler package did.

I use the separate else clause to indicate the "clocked"
part for VHDL template transformation. To make the difference,
I had to introduce a very ugly hack: I detect the column offset
of the test body. If someone has a better idea, let me know,
but I really have to move on for now!

I have pushed all patches to the development branch.

Jan

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