Re: [myhdl-list] Records in VHDL and MyHDL

[Jian L. <jia...@go...>]

On Sat, Jun 19, 2010 at 9:47 AM, Jan Decaluwe <ja...@ja...> wrote:

> Sigve Tjora wrote:
> > Hi!
> >
> > I generate VHDL from MyHDL and when the design has some size, it becomes
> > tedious and error prone to connect all the signals. Is it possible to
> > generate VHDL that uses VHDL-records to group related signals together
> > in the port-list of the generated VHDL code?
>
> Conversion hasn't support for something like this at this moment.
>
> One problem is that I want a solution that works for both Verilog
> and VHDL, as I want to address the whole audience. Therefore,
> I am more thinking about something like interfaces, that then
> would "disappear" in the converted output.
>
> BTW, to avoid connection tediousness, I typically use another
> solution currently. I give ports and signals at the highest
> level of hierarchy unique names, and declare them in
> separate modules. I then import them in the namespace,
> and use a function that does name-based lookup to make
> the connections automatically, based on the interface
> of a module.
>
>
Why not let conversion do the trick? How about a Interface class?
It's contents could be flattened with underscore and it's logic will be
translated
into verilog task or vhdl procedure?

Jan
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>    Python as a HDL: http://www.myhdl.org
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>
>
>
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