[myhdl-list] Records in VHDL and MyHDL

[Sigve T. <si...@tj...>]

Hi!

I generate VHDL from MyHDL and when the design has some size, it becomes
tedious and error prone to connect all the signals. Is it possible to
generate VHDL that uses VHDL-records to group related signals together in
the port-list of the generated VHDL code?

Sigve