Re: [myhdl-list] elif + toVHDL function

[Patrick <pat...@gm...>]

Thank you for your quick reply and for the link.
I haven't used VHDL in a while and I didn't stop to think about the
difference between verilog/VHDL sensitivity lists.

Thanks,
Patrick

On Mon, Mar 29, 2010 at 3:15 PM, Jan Decaluwe <ja...@ja...> wrote:

> patrick wrote:
>
> >
> > I have a question on myHDL's conversion capabilities:
> > When I use a 'elif some_condition:' statement and try to translate it
> > to VHDL I get the following error:
> >
> > myhdl.ConversionError: in file regp2p.py, line 15:
> >     no else test
> >
> > With the toVerilog function the translation works fine.
> >
> > Is a 'elif some_condition:' statement treated differently by the
> > toVHDL function (than by the toVerilog function) or is a 'elif
> > some_condition:' statement in myHDL something other than a 'else: if
> > some_condition:' statement?
>
> The basic issue is explained here:
>
> http://www.myhdl.org/doc/0.6/whatsnew/0.6.html#template-transformation
>
> It may be possible to make template transformation more
> sophisticated and handle code such as yours. However, the
> workaround for now is to put the clock-triggered part of
> the logic in the "else" clause, as you found out.
>
> Jan
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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