Re: [myhdl-list] elif + toVHDL function

[Jan D. <ja...@ja...>]

patrick wrote:

> 
> I have a question on myHDL's conversion capabilities:
> When I use a 'elif some_condition:' statement and try to translate it
> to VHDL I get the following error:
> 
> myhdl.ConversionError: in file regp2p.py, line 15:
>     no else test
> 
> With the toVerilog function the translation works fine.
> 
> Is a 'elif some_condition:' statement treated differently by the
> toVHDL function (than by the toVerilog function) or is a 'elif
> some_condition:' statement in myHDL something other than a 'else: if
> some_condition:' statement?

The basic issue is explained here:

http://www.myhdl.org/doc/0.6/whatsnew/0.6.html#template-transformation

It may be possible to make template transformation more
sophisticated and handle code such as yours. However, the
workaround for now is to put the clock-triggered part of
the logic in the "else" clause, as you found out.

Jan

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