Re: [myhdl-list] Xilinx ISE and MyHDL

[Jan D. <ja...@ja...>]

Jan Decaluwe wrote:
> Mike Gill wrote:
>> Jan Decaluwe <jan <at> jandecaluwe.com> writes:
>>
>>> Mike Gill wrote:
>>>> Hi,
>>>>
>>>> It is very attractive for the entire source code for a Xilinx ISE project 
>> to be 
>>>> managed in Python via myHDL. This needs Xilinx chip features like clock 
>>>> generators and RAM to be defined in Python. Is this possible, and what is 
>> the 
>>>> best approach?
>>> In many cases, RAMs can be inferred from technology-independent
>>> RTL code, which is the preferred approach if it works.
>>>
>>> To instantiate technology-specific modules, you can use the
>>> __verilog__ or __vhdl__ hook. For simulation purposes,
>>> describe the functionality as usual. The convertor
>>> will ignore that code and use the appopriate hook if it exists.
>>>
>>> See:
>>>
>>> http://www.myhdl.org/doc/0.6/manual/conversion.html#user-defined-code
>>>
>> Thanks for reply
>>
>> Making ROM and distributed RAM is easy, but so far no luck with block RAM, and 
>> am afraid I can't work out from the manual section "User-Defined code" if and 
>> how to include a complete VHDL module such as made by an ISE wizard, or whether 
>> the code has to be copied and pasted, and in which case what (I am hoping MyHDL 
>> means not having to learn VHDL or Verilog in any detail)
> 
> The only thing what you have to include is the VHDL or Verilog instantation of
> the module. (The part about instantiation in VHDL or Verilog, you'll have to learn).
> 
> When your have made a macro, think about how you would instantiate that in
> another Verilog or VHDL design. Paste such an instantiation into a string
> assigned to __vhdl__ or __verilog__ in your MyHDL code.
> 
> The remaining thing is the way to attach MyHDL signals to the ports in your
> instantiation. Instead of having actual Verilog or VHDL signal names in your
> instantiation, you use Python format strings referring to MyHDL signals. E.g.
> instead of "clock" you would use "%(clock). (I think this should be clear from
> the examples, even though they don't show instantiations.)
> 
> Now after conversion, your code would contain the instantiation with the 
> appropriate signals names filled in by the convertor.
> 
> Hope this helps?

Let me add to my reply above that I was answering your question related
to user-defined code. I didn't intend to advocate that approach, certainly
not in this case.

As others have pointed out, I don't think user-defined code is the best option
for block ram. Back end tools should be able to infer that from a
technology-independent description.

Personally I would limit user-defined code for those cases were inference
by a synthesis tool or other back-end tools really isn't possible.

Jan

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