Re: [myhdl-list] Xilinx ISE and MyHDL

[Kevin S. <sta...@gm...>]

I am surprised you can't get Xilinx ISE to instantiate Block RAM.  I am
very, very new to MyHDL and haven't done much yet other than follow the
tutorials, but I come from a strong VHDL background and have used all the
big FPGA vendors in projects: Xilinx, Altera, and Actel.

I have no problem getting Xilinx ISE to instantiate block ram with VHDL code
as simple as:

-- declaration of fifoMem
type FifoMemType is array(0 to DEPTH-1) of std_logic_vector(dataW'range);
signal fifoMem : FifoMemType;

-- code snippet of usage of fifoMem
process (clkW)
begin
  if (rising_edge(clkW)) then
    if (rstW = '1') then
      fifoMem <= (others => (others => '0'));
    else
      if (we = '1' and full = '0') then
        fifoMem(conv_integer(addrW'length-2 downto 0))) <= dataW;
      end if;
    end if;
  end if;
end process;

-- do something similar for a read.

So, you see, you can't just create an array of std_logic_vectors, and your
synthesis tool should pick out a Block RAM.  I use Synplify Pro (not XST) so
it is possible XST isn't as capable, but Synplify Pro seems to have no
problem mapping block ram to an RTL implementation of an async FIFO.

I would think that a MyHDL implementation of something similar should
produce synthesizable VHDL or Verilog that would properly map to a Block RAM
upon elaboration.

Can anyone with more MyHDL experience corroborate this?  If you could write
a working memory in MyHDL I could try synthesizing it in Synplify Pro to see
what happens...

Kevin

On Mon, Feb 22, 2010 at 9:42 AM, Mike Gill <zen...@ze...> wrote:

> Jan Decaluwe <jan <at> jandecaluwe.com> writes:
>
> >
> > Mike Gill wrote:
> > > Hi,
> > >
> > > It is very attractive for the entire source code for a Xilinx ISE
> project
> to be
> > > managed in Python via myHDL. This needs Xilinx chip features like clock
> > > generators and RAM to be defined in Python. Is this possible, and what
> is
> the
> > > best approach?
> >
> > In many cases, RAMs can be inferred from technology-independent
> > RTL code, which is the preferred approach if it works.
> >
> > To instantiate technology-specific modules, you can use the
> > __verilog__ or __vhdl__ hook. For simulation purposes,
> > describe the functionality as usual. The convertor
> > will ignore that code and use the appopriate hook if it exists.
> >
> > See:
> >
> > http://www.myhdl.org/doc/0.6/manual/conversion.html#user-defined-code
> >
>
> Thanks for reply
>
> Making ROM and distributed RAM is easy, but so far no luck with block RAM,
> and
> am afraid I can't work out from the manual section "User-Defined code" if
> and
> how to include a complete VHDL module such as made by an ISE wizard, or
> whether
> the code has to be copied and pasted, and in which case what (I am hoping
> MyHDL
> means not having to learn VHDL or Verilog in any detail)
>
> I'd be grateful for an example. You seem to have a preference for Verilog -
> is
> this true?
>
> MyHDL is a terrific idea, as is Python itself, but not many people are
> willing
> to strain their brains with new ideas, and need a lot of help and
> encouragement. How to use MyHDL in the design flow would help a lot, and
> examples of complete projects. DLP Design make a low cost Xilinx fpga
> module
> that is good for training, and it is easy to re-base their example projects
> on
> MyHDL (and talk to the module with a Python GUI)
>
> The "flat" Verilog or VHDL file output means the ISE schematic has no
> useful
> hierarchy for complete designs. I find myself converting/synthesising
> individual blocks to see what each looks like, before assembling the whole
> design. MyHDL is a very fast approach and complicated stuff can be put
> together
> very quickly.
>
> Regards
>
> Mike
>
>
>
>
>
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-- 
Kevin R. Stanton
c | 734•846•3915
e | sta...@gm...