Re: [myhdl-list] verilog conversion issue (discrepancy between Python2.5 and 2.6)

[Jose I. V. <jo...@dt...>]

Hi,
there are two versions of this core:

using external ram at the ldc display:
http://www.opencores.org/websvn,filedetails?repname=wb_lcd&path=%2Fwb_lcd%2Ftrunk%2Fmyhdl%2Fwb_lcd_workspace_ramless%2Fworkspace%2Flcd_display%2Fsrc%2Flcd_display.py

using an internal ram block to store display contents (quicker and bigger):
http://www.opencores.org/websvn,filedetails?repname=wb_lcd&path=%2Fwb_lcd%2Ftrunk%2Fmyhdl%2Fwb_lcd_workspace%2Fworkspace%2Flcd_display%2Fsrc%2Flcd_display.py


José Ignacio Villar <jo...@dt...>
Departamento de Tecnología Electrónica
Escuela Técnica Superior de Ingeniería Informática
Universidad de Sevilla
Avda. Reina Mercedes, s/n
41012 - Sevilla (Spain)

Tlf: 954 55 99 62
Fax: 954 55 27 64



On Wed, Feb 10, 2010 at 1:03 AM, Jan Decaluwe <ja...@ja...> wrote:

> Jose Ignacio Villar wrote:
> > Hi all,
> > some time ago i developed an lcd controller using Myhdl 0.6 and Python
> > 2.5 that can be found on opencores
> > (http://www.opencores.org/project,wb_lcd).
>
> I was trying to browse through your myhdl code in the
> svn browser, but I don't seem to find it, can
> you tell me were it is?
>
> Thanks
>
> Jan
>
>
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>    Python as a HDL: http://www.myhdl.org
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>
>
>
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