[myhdl-list] verilog conversion issue (discrepancy between Python2.5 and 2.6)

[Jose I. V. <jv...@gm...>]

Hi all,
some time ago i developed an lcd controller using Myhdl 0.6 and Python 2.5
that can be found on opencores (http://www.opencores.org/project,wb_lcd).

This week I updated my system to Python 2.6 and bleeding edge branch of
Myhdl. But when I tried to convert it to Verilog it started shouting because
of some lines that were already working with Python 2.5.

The problem is about the following kind of generators:

    @always_comb
    def output_tx_or_init_select():
        testOut.next = (state == t_State.SEARCH) | (state ==
t_State.CONFIRM)

that in Python 2.6 used to generate the following verilog code:

assign testOut = ((state == 3'b001) | (state == 3'b010));

Everything fixed up by changing "|" operator by an Python "or":

    @always_comb
    def output_tx_or_init_select():
        testOut.next = (state == t_State.SEARCH) or (state ==
t_State.CONFIRM)

and now it generates:

assign testOut = ((state == 3'b001) || (state == 3'b010));

Although both are working in my fpga, and from the verilog point of view (If
I'm not mistaken) are functionally equivalent, should Python 2.6 be able to
extract correct code for the first approach?
I'd like to hear what experts think about it before spending several days
digging in the code to find taht I was wrong.

Kind Regards,
Jose Ignacio Villar.

José Ignacio Villar <jo...@dt...>
Departamento de Tecnología Electrónica
Escuela Técnica Superior de Ingeniería Informática
Universidad de Sevilla
Avda. Reina Mercedes, s/n
41012 - Sevilla (Spain)

Tlf: 954 55 99 62
Fax: 954 55 27 64