Re: [myhdl-list] cver fails Verilog power operator

[Jan D. <ja...@ja...>]

Christopher Felton wrote:

> I wonder if any commercial (maybe the commercial version of cver) would 
> be interested in giving you a license for there simulator.  Simply to 
> get the exposure, "Company XXX Verilog/VHDL simulator compatible with 
> MyHDL".  Seems like a small cost for a company to provide a license or 
> two and possibly receive some additional exposure.

There would have to be a business reason for them, which is not
that obvious even (or especially) if MyHDL would be more widely used.
I believe our first such allies could be FPGA vendors, but probably
they will move only when their customers start asking for it.

> I am all for the open-source versions (maybe the open-source should use 
> MyHDL for unit-testing their simulators) but there appears to be some 
> limitations.

It wouldn't be too difficult for me to get access to commercial
licenses to check and add MyHDL support, by asking some befriended
companies. Here is why I've not done that:

- Cosimulation support for other simulators is an ideal task that
could be done and supported by someone else.
- I still have my hopes set on Icarus Verilog, of course one has to file
bug reports in case of problems.
- The best target for MyHDL is the most limited simulator or back-end
tool that still works reasonably (this is a compromise), because that
creates most value for a user; moreover it then certainly works for
more powerful tools.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com