Re: [myhdl-list] Co-simulation and generating VCD with $dumpvars

[Christopher F. <chr...@gm...>]

On 1/18/10 10:34 AM, Christopher Felton wrote:
>
> [background]
> Given the previous thread I realize that there are some Co-simulation
> issues with the Open-Source Verilog simulators.  With my development I
> have been jumping straight to hardware (not because of the limitations
> but mainly because it worked and/or laziness).  Everything has been
> working great.
>
> I did hit a point where the synthiszed design doesn't appear to match
> the simulated design (verified in lab with scope and compared simulation
> waveforms).  At that point I was attempting to verify with
> co-simulation.  The co-simulation has been generating mismatches.
>
> [dumpvars ??]
> In attempt to debug the co-simulation mismatches I wanted to create a
> VCD to look at the Verilog waveforms.  I tried adding the Verilog
> $dumpvars to my generated Verilog (using the __verilog__ in my top-level
> MyHDL).  This appeared to break the co-simulation, I would get an
> exception in the Co-simulation pipe read (possibly the Verilog simulator
> not responding?).
>
> Has anyone else seen similar behavior?  Is there a better method to
> produce a VCD from the co-simulated Verilog?
>

If I put the dumpvars in the generated testbench it works.  But I have 
to manually add the $dumpvars each time or change the conversion code.

Added to the end of the generated Verilog testbench interface, tb_*

initial begin
   $dumpfile("<dumpfile.vcd>");
   $dumpvars;
   $dumpvars(0, dut);
end

Still curious if this has been accomplished by some other mechanism.

.chris