Re: [myhdl-list] cver fails Verilog power operator
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jandecaluwe
From: Jan D. <ja...@ja...> - 2010-01-18 09:51:53
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Christopher L. Felton wrote: > Cver appears to fail the Verilog power operator? Has anyone else seen this? > > > GPL CVER Version > """ > GPLCVER_2.12a of 05/16/07 (Mac OSX). > Copyright (c) 1991-2007 Pragmatic C Software Corp. > All Rights reserved. Licensed under the GNU General Public License > (GPL). > """ > > Example: > > _MyHDL_ > @always_comb > def rtl_wp(): > wp_p1.next = (wp + 1) % 2**C_ASZ > > _Convert Verilog_ > assign spi0_txFifo_wp_p1 = ((spi0_txFifo_wp + 1) % (2 ** 3)); > > > > My work around was to change the my MyHDL code to compute the mod value. > _MyHDL_ > AddressMod = 2**C_ASZ > @always_comb > def rtl_wp(): > wp_p1.next = (wp + 1) % AddressMod > > > The "**" is a Valid power operator in Verilog and Icarus Verilog appears > to handle it ok (as well as the synthesis tools). I was wondering if a > warning should be added? > > Side note I have been using Icarus and Cver. I ran into another error > using Icarus (probably self induced) and it wasn't clear what the > problem was so I tried Cver to hopefully shed some light when I hit the > problem. Unfortunately MyHDL has come to a point where neither Icarus nor Cver runs the conversion test suite completely without errors, though I have every reason to believe the generated Verilog is correct. The proper way is of course to file bug reports. However, for Cver this doesn't make sense anymore because open source development has stopped. The power operator is a special case. It was added in Verilog 2001. Cver doesn't support it and apparently never will, but recent versions of Icarus support it. However, when I was working on the convertor for it, it didn't work properly for neither Cver, Icarus and GHDL, so I dropped working on the unit tests at the time. I just checked again and immediately run into issues with Verilog, so the convertor output is probably buggy. (Probably low level bit width issues again.) This will have to be looked at in detail again. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com |