Re: [myhdl-list] fxintbv dependency on dspsim

[Jan D. <ja...@ja...>]

Felton Christopher wrote:
> On Jan 15, 2010, at 2:46 AM, Jan Decaluwe wrote:
> 
>> Christopher L. Felton wrote:
>>> Jan Decaluwe wrote:
>>>> I'm not a fixed-point specialist, but am I correct in thinking that
>>>> things would be considerably simpler if there would a fixed point
>>>> datatype that we could map to in VHDL/Verilog?
>>>>
>>>> I seem to have read that such a (synthesizable) datatype exists for
>>>> VHDL, but not yet for Verilog. But even it's VHDL-only, it seems  
>>>> like
>>>> an interesting path to investigate?
>>> I believe there is a fixed-point type in the latest standard of VHDL
>>> (VHDL-2007).  I don't know much more about the new VHDL type.  If  
>>> it has
>>> been ratified, supported in tools, etc.
>>>
>>> From a quick search, the VHDL fixed-point type doesn't do
>>> auto-promotion (what size should the result be).  The new types
>>> introduce the negative index in ranges (???).  I don't think it  
>>> supports
>>> all features the lib attempts to support.
>>>
>>> Regardless, I think this is one of highlights of MyHDL to handle  
>>> these
>>> kinds "types".  I think the current MyHDL approach gives the design  
>>> much
>>> more flexibility.  A designer might not always want the "default"  
>>> rules
>>> for handling fixed-point.  If mapped to the VHDL type I think there
>>> would be a "collision" of rules and loss of control.
>> I'm intrigued by these statements, please enlighten me.
> 
> Which statements?  My incomplete understanding of the VHDL fixed-point  
> support?   Or the flexibility of MyHDL to handle fractional numbers  
> without changing the core package?

I was referring to your statement that "A designer might not always
want the "default" rules for handling fixed point".

Regardless of the mechanism to make fixed point available with MyHDL,
I would hope, naively perhaps, that we can find a single way to make
everybody happy. But again, I've not yet studied the subject in depth.


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