[myhdl-list] cver fails Verilog power operator

[Christopher L. F. <chr...@gm...>]

Cver appears to fail the Verilog power operator?  Has anyone else seen this?


GPL CVER Version
"""
GPLCVER_2.12a of 05/16/07 (Mac OSX).
Copyright (c) 1991-2007 Pragmatic C Software Corp.
   All Rights reserved.  Licensed under the GNU General Public License 
(GPL).
"""

Example:

_MyHDL_
     @always_comb
     def rtl_wp():
         wp_p1.next = (wp + 1) % 2**C_ASZ

_Convert Verilog_
     assign spi0_txFifo_wp_p1 = ((spi0_txFifo_wp + 1) % (2 ** 3));



My work around was to change the my MyHDL code to compute the mod value.
_MyHDL_
AddressMod = 2**C_ASZ
@always_comb
     def rtl_wp():
         wp_p1.next = (wp + 1) % AddressMod


The "**" is a Valid power operator in Verilog and Icarus Verilog appears 
to handle it ok (as well as the synthesis tools).  I was wondering if a 
warning should be added?

Side note I have been using Icarus and Cver.  I ran into another error 
using Icarus (probably self induced) and it wasn't clear what the 
problem was so I tried Cver to hopefully shed some light when I hit the 
problem.

.chris