Re: [myhdl-list] fxintbv dependency on dspsim

[Felton C. <chr...@gm...>]

On Jan 15, 2010, at 2:46 AM, Jan Decaluwe wrote:

> Christopher L. Felton wrote:
>> Jan Decaluwe wrote:
>>> I'm not a fixed-point specialist, but am I correct in thinking that
>>> things would be considerably simpler if there would a fixed point
>>> datatype that we could map to in VHDL/Verilog?
>>>
>>> I seem to have read that such a (synthesizable) datatype exists for
>>> VHDL, but not yet for Verilog. But even it's VHDL-only, it seems  
>>> like
>>> an interesting path to investigate?
>>
>> I believe there is a fixed-point type in the latest standard of VHDL
>> (VHDL-2007).  I don't know much more about the new VHDL type.  If  
>> it has
>> been ratified, supported in tools, etc.
>>
>> From a quick search, the VHDL fixed-point type doesn't do
>> auto-promotion (what size should the result be).  The new types
>> introduce the negative index in ranges (???).  I don't think it  
>> supports
>> all features the lib attempts to support.
>>
>> Regardless, I think this is one of highlights of MyHDL to handle  
>> these
>> kinds "types".  I think the current MyHDL approach gives the design  
>> much
>> more flexibility.  A designer might not always want the "default"  
>> rules
>> for handling fixed-point.  If mapped to the VHDL type I think there
>> would be a "collision" of rules and loss of control.
>
> I'm intrigued by these statements, please enlighten me.

Which statements?  My incomplete understanding of the VHDL fixed-point  
support?   Or the flexibility of MyHDL to handle fractional numbers  
without changing the core package?

> With intbv, I have tried (and I believe not without success) to  
> implement
> the single way to do it "right". The basic idea is to let it behave
> as mathematical integers do (and there is little controversy about  
> that.)
> The convertor implements this in Verilog and VHDL with lower
> level types by using type casts and resizings.
> (In contrast, there is a lot of controversy about how such lower level
> types should behave!)

What I am trying to suggest and promote.   Is that, as you mention,  
the intbv handles the integers fine.  WIth fixed point we are trying  
to use fractional numbers like 3.141592.  The MyHDL architecture has a  
nice mechanism to do this.  During elaboration we can perform the  
necessary steps to get our integer representation of our fractional  
number.  Then all the conversion, simulation, etc is handled by the  
intbv.

>
> What you suggest is that with fixed point, something like that would
> not be possible: you suggest that there isn't "one good way to do it".
> I'd like to understand better why you think that is so.

I am doing a poor job of communicating.  I do think adding support  
(external packages) for higher types (fixed-point, floating-point) is  
possible!  Exactly as you say, instead of mapping to the VHDL type in  
MyHDL first map to intbv because the rules are clear!  The goal of the  
fixed point package is to give the developer the tools to map a  
fractional number to an integer representation.  Then intbv handles  
the rest.

The issues with these higher types is discovering a "user friendly"  
mechanism.  I have run across some issues, not necessarily MyHDL  
issues, but things I wanted to do in the elaboration and have not been  
able to do.

Hope that helps explain a little better?


>
> Jan
>
>
> -- 
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>    Python as a HDL: http://www.myhdl.org
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>
>
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