Re: [myhdl-list] fxintbv dependency on dspsim

[Jan D. <ja...@ja...>]

Christopher L. Felton wrote:
> Jan Decaluwe wrote:
>> I'm not a fixed-point specialist, but am I correct in thinking that
>> things would be considerably simpler if there would a fixed point
>> datatype that we could map to in VHDL/Verilog?
>>
>> I seem to have read that such a (synthesizable) datatype exists for
>> VHDL, but not yet for Verilog. But even it's VHDL-only, it seems like
>> an interesting path to investigate?
> 
> I believe there is a fixed-point type in the latest standard of VHDL 
> (VHDL-2007).  I don't know much more about the new VHDL type.  If it has 
> been ratified, supported in tools, etc.
> 
>  From a quick search, the VHDL fixed-point type doesn't do 
> auto-promotion (what size should the result be).  The new types 
> introduce the negative index in ranges (???).  I don't think it supports 
> all features the lib attempts to support.
> 
> Regardless, I think this is one of highlights of MyHDL to handle these 
> kinds "types".  I think the current MyHDL approach gives the design much 
> more flexibility.  A designer might not always want the "default" rules 
> for handling fixed-point.  If mapped to the VHDL type I think there 
> would be a "collision" of rules and loss of control.

I'm intrigued by these statements, please enlighten me.
With intbv, I have tried (and I believe not without success) to implement
the single way to do it "right". The basic idea is to let it behave
as mathematical integers do (and there is little controversy about that.)
The convertor implements this in Verilog and VHDL with lower 
level types by using type casts and resizings.
(In contrast, there is a lot of controversy about how such lower level
types should behave!)

What you suggest is that with fixed point, something like that would
not be possible: you suggest that there isn't "one good way to do it".
I'd like to understand better why you think that is so.

Jan


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com