Re: [myhdl-list] fixed_point library and VHDL generation

[Christopher F. <chr...@gm...>]

Jan L.

Thanks for the input and glad to hear you are having fun with myhdl.  I
regret that I have not had more time to make the fixed_point library more
usable and flexible.  Thanks for keeping interest in some of the projects
(more inlined).

On Tue, Jan 12, 2010 at 12:33 PM, Jan Langer <jan...@et...
> wrote:

> Hi all,
> i have solved my issues regarding Christopher's fixed_point library :-)
>
> There is one more thing I want to share. The following situation:
>
> a = Signal(fxintbv(0,Q=(0,16))
> b = Signal(fxintbv(0,Q=(0,16))
>
> i = 2
>
> @always(clk.posedge)
> def beh():
>        if b < 0:
>                d = 1
>        else:
>                d = -1
>        a.next = a - ((d*b) >> i)
>
> The way I made that code working correctly is just casting a to int: a.next
> = a*1 - ((d*b) >> i)
>

The actual problem is that I relied on the lower level intbv to handle the
logical and shift operators. The lower level intbv operators simply return
an 'int' type.  I need to add the operator overloads (all of them) to the
fxintbv and have them return fxintbv type.  They you will not get the error.
 I will try to have the 0.4 release ASAP to fix this.


>
> However, this is not the correct way, but I was too lazy to do it right,
> and I am still not really sure, what the correct way is.
>
> The second thing I want to share were two issues during VHDL synthesis.
> First, the assignments of constants of bit lengths greater 32 does not work.
> I will append a patch for that, that uses bit strings in this case.
>
>
>
>
>
>  Second, local variables in processes hide global variables on top level.
> The following code generates wrong VHDL:
>
> ---------------------
>
> from myhdl import *
>
> def Block2(clk,b):
>        @always(clk.posedge)
>        def beh():
>                a = 4
>                b.next = b + a
>
>        return instances()
>
> def Block1(clk):
>        a = Signal(intbv(0)[4:])
>
>        b2 = Block2(clk,a)
>
>        return instances()
>
> clk = Signal(bool(0))
> toVHDL(Block1,clk)
>
> ----------------------
>
> You can work around that problem easily by giving unique names, but its
> quite annoying and hard to prevent when using third party blocks.
>
> Apart from me always posting about problems or issues I do not understand,
> I think myhdl is just a great effort in the direction I personally see
> hardware development evolve in the future.
>
> Best regards,
> Jan
>
> --
> Jan Langer
> (Telefon) +49-371-531-33158 / (PGP) F1B8C1CC
> Schaltkreis- und Systementwurf / TU Chemnitz
>
>
>
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