Re: [myhdl-list] [PATCH] Remove redundant copy operators

[Jan D. <ja...@ja...>]

Benoît wrote:

> Hi Jan,
> 
> Of course you are right, thinking about it, I guess the only thing  
> that could justify those statements above is my hardware mind. That  
> same nasty one that makes me think ahead of the cost (latch, wire,  
> clock cycles) of each line I'm writting. That's the way I learnt to  
> write VHDL. Only, this does not apply to MyHDL.

I think VHDL and MyHDL are much more similar than you suggest here.
You could perfectly write MyHDL with the "think hardware" mindset
you describe.

Personally, I just don't think that "think hardware" is the most
effective design strategy. I prefer "synthesis-aware" design where
you raise the abstraction level as much as possible without
jeopardizing efficiency. You still have to know about hardware,
but more importantly, you have to understand what a synthesis
tool can and cannot do. Many "hardware thinkers" don't fully
appreciate this. They fail to see elegant, efficient solutions,
just because they can't visualize them readily in hardware.

I have written lots of VHDL since 1990 and I have always used
the "synthesis-aware" strategy. So I really don't think it's
a matter of HDL language, but of mindset.

Of course, some design decision in MyHDL are inspired by my
personal preferences, e.g. the intbv class. But I don't think
that makes an essential difference here.

> This just lead to one question ? How to write MyHDL code ? Depending  
> on what you're looking for I guess.

I do it exactly like I did with VHDL: the highest possible abstraction
level, but synthesis-aware. In practice this means e.g.

- preference for the clocked process template as a default
- no separation between "control" and "data" logic
- preference for variables inside processes, including for register inference

However, my guess is that many MyHDL users don't do it like that,
and MyHDL works for them too.

Jan



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Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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