Re: [myhdl-list] [Announce] Jan on HDL Design

[Christopher F. <cf...@uc...>]

On Wed, Nov 11, 2009 at 8:08 AM, Jan Decaluwe <ja...@ja...> wrote:

> Christopher Felton wrote:
> > Thanks for the link, I am always interested in your thoughts and
> > opinions.  This leads to an interesting question, which is your
> > preference,  MyHDL design or VHDL with modern development tools (hope
> > that doesn't put you on the spot)?
>
> Without constraints I would obviously choose MyHDL as the first option,
> if only to get the bugs out of my own stuff :-)
>
> However, note that even then I will likely need VHDL in the process:
> as the result from MyHDL, to integrate with 3rd party stuff, to
> synthesize from. From now on, I would always use Sigasi HDT to
> support that work. Note also that I could use refactoring e.g. to
> create hierarchy out of a flat design from the MyHDL convertor.
>
> MyHDL and VHDL should not be viewed as opponents. MyHDL's main
> inspiration is obviously VHDL. MyHDL can be viewed as VHDL's
> "scripting companion". I have a lot to thank to VHDL, but I've
> written so much of it already that it's also a simple matter
> of not getting bored! It's true however that Sigasi HDT makes
> it much more fun again. It avoids most of the boring stuff.
>
> I don't think my own situation is that relevant however. I believe
> that MyHDL (or at least its concepts) has a good future in the
> longer term, but there's also the short and medium term to take
> care of. There you have all kind of constraints, personal
> preferences, company policies etc. Realistically people in
> different situations need different solutions, and for me
> it's not a contradiction to work on various fronts of progress.
>
> Jan
>
> --
>

Thanks for the reply, btw I agree totally.  Based
on constraints, circumstances, ideologies, etc can/will drive the
technology.  One thing I did find interesting was the idea of refactoring
the generated VHDL.  That appears breaks the philosophy previously held, the
output is more of an intermediate form not required to be tampered with.
 The idea of not modifying the generated HDL in itself doesn't prevent
integration with legacy VHDL/Verilog.  So, is it more as a debug / analysis
tool?  The refactoring would have to be complete on each new generation of
the hdl, correct?

Thanks again,
.Chris