Re: [myhdl-list] delay/timing specification & constrains (setup/hold), asserts

[Jan D. <ja...@ja...>]

john smith wrote:
> Hi Jan,
>  
> Recently I started looking at myHDL/Python for HW 
> simulation/verification and I 'd like to know 
> if timing/delay specifications and checks (e.g. setup, hold), possibly 
> asserts (which should not be hard considering the python exceptions 
> support) related functionality is supported.
>  
> I looked through myHDL manual and examples but I couldn't find anything 
> related.
> If supported, I'd appreciate you (or others) mentioning the 
> document/sections/examples, if not, do you have any plans?

No plans.

Some considerations:

Obviously MyHDL is strongly inspired by my approach to
digital design. In that appproach, RTL design and higher
is the front-end, gate-level is part of the back-end and
only used for the verification of synthesis and physical
implementation.

I believe there are many things wrong with the traditional
tools for RTL design. However, little is wrong with the
gate-level stuff, hence not much can be done to improve things.
That's why MyHDL focusses on RTL and higher.

Also, my favourite approach to timing verification is not gate
level simulation, but timing analysis.

Finally, MyHDL is intrinsically much slower than compiled
simulations (although google is putting its weight behind
a substantial improvement.) I think this is acceptable at
the design front-end, given what you get back in expressive
power and flexibility. However, such a consideration doesn't
hold for gate-level verification: raw performance is all
what counts there.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
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