Re: [myhdl-list] delay/timing specification & constrains (setup/hold), asserts

[Christopher L. F. <chr...@gm...>]

from myhdl import *


def simple_ex(clk, rd, wr, din, dout):
    _d = Signal(intbv(0)[8:])

    @always(clk.posedge)
    def rtl_data():
        if rd and wr:
            assert False, "Invalid Operation"
        if rd:
            dout.next = _d
        elif wr:
            _d.next = din

    return instances()


def test():

    clk  = Signal(False)
    rd   = Signal(False)
    wr   = Signal(False)
    din  = Signal(intbv(0)[8:])
    dout = Signal(intbv(0)[8:])

    dut = simple_ex(clk, rd, wr, din, dout)
    
    @always(delay(1))
    def tb_clk_gen():
        clk.next = not clk

    @instance
    def tb_main():
        din.next  = 0xCE
        rd.next   = False
        wr.next   = True
        yield delay(4)
        rd.next   = True
        wr.next   = False
        yield delay(4)
        assert dout == 0xCE, "Testbench FAILED, Expected dout == 0xCE got 0x%02X" % (dout)
        print "Data check OK"
        
        din.next  = 0xBA
        rd.next   = True
        wr.next   = True

        yield delay(4)
        assert False, "Should not get this far, module should assert and fail"
        # Alternative is to catch the assert and verify an assert occurred

    return instances()

if __name__ == '__main__':
    tb = test()
    sim = Simulation(tb)
    sim.run()