Re: [myhdl-list] List of Signals in an always_comb

[Jan D. <ja...@ja...>]

Thanks, I have applied the patch and pushed it to the public repo's.


Felton Christopher wrote:
> I came across a possible issue.  I had created a design that had used a 
> list of signals in an always_comb generator.  The conversion determined 
> that the alway_comb generator was of type "SIMPLE" and the resulting 
> Verilog generated "assign" for signal array.  In short the generated 
> Verilog is not valid Verilog.
> 
> I have attached a simple example of the MyHDL and the generated Verilog 
> (example_fail.v).  I also attached a patch for a possible fix (if it is 
> determined this is an issue).  The fix uses the same method to determine 
> if a ROM is being generated (hasRom) and the generated Verilog with the 
> patch (example.v).
> 
> 
> 
> ------------------------------------------------------------------------
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> Thanks
> 
> Chris
> 
> 
> ------------------------------------------------------------------------
> 
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