[myhdl-list] Bus Transaction Models and Testbenches

[Felton C. <chr...@gm...>]

I have created a simple bus model to interface to my design.  I have a  
generator that will pull data from a FIFO (python list).  And a bunch  
of functions that write and read to the FIFO.

My testbench uses the functions (and generators) to interface to the  
DUT.  The following is an example:

-----------
     gen = fx2Model.WriteAddress(0x0103, 0xAA)
     yld = gen.next()
     while yld is not None:
         yield yld
         yld = gen.next()
...
     TracePrint('Wait for data in read fifo')
     while not fx2Model.IsData(fx2Model.EP8, 5):
         yield delay(2*fx2Model.IFCLK_TICK)

     for dat in test_data1:
         rdata = fx2Model.Read(fx2Model.EP8)
         assert rdata == dat, \
         "Testbench FAILED return data %x expected %x" % (rdata, dat)

----------

My questions (issue) is that the transactors have many steps (do  
multiple "things") and need to "yield".  A yield, relinquish to the  
simulation engine, can only be issued at the top testbench generator.   
The functions (generators) that encapsulate the bus transactions only  
return what to "wait for".  But I would like my testbenches to be read  
as:

----------
     fx2Model.WriteAddress(0x0103, 0xAA)
     fx2Model.Read(fx2Model.EP8, rdata)
----------

I don't know how to achieve the desired second example because the  
model functions (generators) would need to yield.  If the yields are  
in the model it will only yield to the top testbench function  
(generator).  Any suggestions or ideas welcome.

I have posted the project on the MyHDL website, more information is  
available here, http://www.myhdl.org/doku.php/users:cfelton:projects:usbp

Thanks
Chris