Re: [myhdl-list] bit-wise or

[Christopher F. <chr...@gm...>]

On Wed, Jul 22, 2009 at 3:42 PM, Patricio Kaplan
<pat...@gm...>wrote:

> Is there an easy way to do what this verilog code does with myhdl?
> wire abc[11:0];
> wire a_bit_set = |abc;
>
> ----------
>
>
BOMK there isn't a similar 1 liner to do a reduction "or" (reduction
anything) in MyHDL.  Since MyHDL uses Python operators there isn't
an equivalent operator to override for such functionality.

But you can use for loops to achieve the same functionality.  And you should
be able to write a function that is synthesizable that can be used
on variable bit-vectors.

Is there a similar "one liner" in VHDL?  How would this be done in VHDL?  I
have always used loops in VHDL.

Chris