Re: [myhdl-list] Programmable LFSR
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Re: [myhdl-list] Programmable LFSR
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From: Christopher F. <chr...@gm...> - 2009-07-20 14:41:24
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You are now creating the constant / static bit-vector during the
elaboration phase (elaboration is great cause you can use all of
Python's power). I think the issue is, the constant bit-vector exists
but what is the hardware representation of the "bitvector". Kinda like
the RAM/ROM modules you posted about earlier. I believe there still
needs to be some component for the bitvector, need a signal and possibly
addition generator that describes what bitvector (or corresponding
signal) is.
First need a signal for the bitvector
sbit = Signal(bitvector)
Instead of if bitvectore[i], use if sbit[i]
And possibly some behavioral definition that states what the sbit is in
hardware (register, combo constants, etc). Example make it a register
@always(clk.posedge)
def rtl_bitvector_reg():
if rst:
sbit.next = bitvector
I didn't test this but hopefully this will helps
Chris
Joseph Cali wrote:
> I tried to use the bitvector approach, but I am not getting a new
> error. I think that I am not using the intbv class correctly in some
> cases, as I have seen this error pop up several times in other MyHDL
> generators that I have written. I also should note that I am using
> the most recent MyHDL from the mercurial repository.
>
> Here is the code
> ---------------------------------------------------------------------
>
> def Galois(out, clk, rst, width=32):
> '''
> Implement a Galois Linear Feedback Shift Register (LFSR).
>
> Parameters
> ----------
> width : integer
> The length of the LFSR
>
> Input Ports
> -----------
> clk : The clock
> rst : Active high reset
>
>
> Output Ports
> ------------
> out : Pseudo-Random word
> '''
> sel_table = width - 3
> polynomial = GALOIS_TABLE[sel_table]
> polynomial = polynomial[1:len(polynomial)-1]
> bitvector = intbv(0)[width:]
> for i in range(0, width):
> if i in polynomial:
> bitvector[i] = 1
> else:
> bitvector[i] = 0
>
>
>
> state = Signal(intbv(0)[width:])
>
> @always(clk.posedge, rst)
> def logic():
> if rst == 1:
> state.next[0] = 1
> else:
> state.next[width-1] = state[0]
> for i in downrange(width-1, 0):
> if bitvector[i]:
> state.next[i] = state[i+1] ^ state[0]
> else:
> state.next[i] = state[i+1]
>
> Joseph
>
>
>
> On Jul 20, 2009, at 4:16 AM, Jan Decaluwe wrote:
>
>> Syntax
>>
>> if in ...
>>
>> is indeed not supported. This is currently not checked, hence the bad
>> stack trace instead of a clear error message.
>>
>> As a workaround, map the polynomial to a bitvector with the significant
>> bits set before using it inside a generator. Then you can use
>>
>> if polynomial[i] ...
>>
>> as the check.
>>
>> Probably you mean state.next[i], not state[i].next.
>>
>> All code inside a generator is converted literally, so you will
>> get a for-loop in the output.
>>
>> Jan
>>
>>
>> Joseph Cali wrote:
>>> I am attempting to parameterize the creation of Galois LFSRs. I
>>> have a table that contains Galois polynomials (a list of tuples
>>> named GALOIS_TABLE). The following is my first attempt at a
>>> solution in MyHDL.
>>>
>>> def Galois(out, clk, rst, width=32):
>>> '''
>>> Implement a Galois Linear Feedback Shift Register (LFSR).
>>>
>>> Parameters
>>> ----------
>>> width : integer
>>> The length of the LFSR
>>>
>>> Input Ports
>>> -----------
>>> clk : The clock
>>> rst : Active high reset
>>>
>>> Output Ports
>>> ------------
>>> out : Pseudo-Random word
>>> '''
>>> sel_table = width - 3
>>> polynomial = GALOIS_TABLE[sel_table]
>>> polynomial = polynomial[1:len(polynomial)-1] # Take the relevant
>>> part of the polynomial
>>>
>>> state = Signal(intbv(0)[width:])
>>>
>>> @always(clk.posedge, rst.negedge)
>>> def logic():
>>> if rst == 1:
>>> state.next[0] = 1
>>> else:
>>> state.next[width-1] = state[0]
>>> for i in downrange(width-1, 0):
>>> if i in polynomial: # This is where the problem occurs, I believe
>>> state[i].next = state[i+1] ^ state[0]
>>> else:
>>> state[i].next = state[i+1]
>>>
>>> @always_comb
>>> def assignments():
>>> out.next = state
>>>
>>> return logic, assignments
>>>
>>>
>>> --------------------------------------------------------------------------------------------------------------------
>>> I do not think the "if i in whatever" syntax is convertible. I was
>>> wondering if anyone had any
>>> suggestions on alternative Python code that would yield a
>>> convertible example. Attempting
>>> to convert the above code gives the following stack trace using
>>> Python 2.6.2:
>>>
>>> File "galois.py", line 147, in <module>
>>> galois = toVerilog(Galois, out, clk, rst, width=18)
>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>> line 124, in __call__
>>> _convertGens(genlist, vfile)
>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>> line 321, in _convertGens
>>> v.visit(tree)
>>> File "/usr/lib/python2.6/ast.py", line 231, in visit
>>> return visitor(node)
>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>> line 1248, in visit_Module
>>> self.visit(stmt)
>>> File "/usr/lib/python2.6/ast.py", line 231, in visit
>>> return visitor(node)
>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>> line 1850, in visit_FunctionDef
>>> self.visit_stmt(node.body)
>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>> line 1599, in visit_stmt
>>> self.visit(stmt)
>>> File "/usr/lib/python2.6/ast.py", line 231, in visit
>>> return visitor(node)
>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>> line 1177, in visit_If
>>> self.mapToIf(node)
>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>> line 1232, in mapToIf
>>> self.visit_stmt(node.else_)
>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>> line 1599, in visit_stmt
>>> self.visit(stmt)
>>> File "/usr/lib/python2.6/ast.py", line 231, in visit
>>> return visitor(node)
>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>> line 1140, in visit_For
>>> self.visit_stmt(node.body)
>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>> line 1599, in visit_stmt
>>> self.visit(stmt)
>>> File "/usr/lib/python2.6/ast.py", line 231, in visit
>>> return visitor(node)
>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>> line 1177, in visit_If
>>> self.mapToIf(node)
>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>> line 1221, in mapToIf
>>> self.visit(test)
>>> File "/usr/lib/python2.6/ast.py", line 231, in visit
>>> return visitor(node)
>>> File "/home/jcali/workspace/myhdl/myhdl/conversion/_toVerilog.py",
>>> line 969, in visit_Compare
>>> self.write(" %s " % opmap[type(node.ops[0])])
>>> KeyError: <class '_ast.In'>
>>>
>>>
>>> --------------------------------------------------------------------------------------------------------------------
>>> For width=18, a Galois polynomial is x^18 + x^11 + 1. The target
>>> Verilog should behave as below:
>>>
>>> module galois18(state, clk, rst);
>>> input clk;
>>> input rst;
>>> output [17:0] state;
>>> reg [17:0] state;
>>>
>>> always @(posedge clk) begin
>>> if(~rst) begin
>>> state <= {state[0], state[17:12], state[11]^state[0], state[10:1]};
>>> end
>>> else begin
>>> state[0] <= 1;
>>> end
>>> end
>>> endmodule
>>>
>>>
>>>
>>> Joseph
>>>
>>> ------------------------------------------------------------------------------
>>> Enter the BlackBerry Developer Challenge
>>> This is your chance to win up to $100,000 in prizes! For a limited
>>> time,
>>> vendors submitting new applications to BlackBerry App World(TM) will
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>>
>>
>> --
>> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>> Python as a HDL: http://www.myhdl.org
>> VHDL development, the modern way: http://www.sigasi.com
>> Analog design automation: http://www.mephisto-da.com
>> World-class digital design: http://www.easics.com
>>
>>
>> ------------------------------------------------------------------------------
>> Enter the BlackBerry Developer Challenge
>> This is your chance to win up to $100,000 in prizes! For a limited time,
>> vendors submitting new applications to BlackBerry App World(TM) will have
>> the opportunity to enter the BlackBerry Developer Challenge. See full
>> prize
>> details at: http://p.sf.net/sfu/Challenge
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> <mailto:myh...@li...>
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>
> Joseph Cali
> ca...@au... <mailto:ca...@au...>
> Graduate Research Assistant
> Auburn University
> Work: 334-844-8257
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